Threefish-256 algorithm implementation on reconfigurable hardware
This article presents both the description and results of the Threefish cryptographic algorithm hardware implementation for encryption process. The implementation of the algorithm was performed by using the iterative round architecture on the FPGA (Field Programmable Gate Array) Virtex-...
| Autor Principal: | Nieto-Ramírez, Nathaly; Ing. Electrónica, Investigador Grupo de Arquitecturas Digitales y Microelectrónica Universidad del Valle Cali, |
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| Otros Autores: | Nieto-Londoño, Rubén Darío; Ph.D. Investigador Grupo Arquitecturas Digitales y Microelectrónica Universidad del Valle Cali, |
| Formato: | info:eu-repo/semantics/article |
| Idioma: | spa |
| Publicado: |
Universidad Santo Tomás. Seccional Bucaramanga
2014
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| Materias: | |
| Acceso en línea: |
http://revistas.ustabuca.edu.co/index.php/ITECKNE/article/view/725 |
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| Sumario: |
This article presents both the description and results of the Threefish cryptographic algorithm hardware implementation for encryption process. The implementation of the algorithm was performed by using the iterative round architecture on the FPGA (Field Programmable Gate Array) Virtex-5 present in the development system XUPV5-LX110T. Place and route results show that the design Threefish-256 iterative round has a throughput of 551Mbps. |
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